October 6-8, 2014
Playa del Carmen, Mexico
Iberostar Tucán and Quetzal Hotel
Sunday, 5 October 2014 |
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Fringe Meetings (by invitation only): |
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14:00 – 15:00 |
IFIP VLSI-SoC Steering Committee Meeting |
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Organizer: Salvador Mir, TIMA, France (Room: OAXACA) |
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15:00 – 17:00 |
IFIP WG 10.5 Meeting |
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Organizer: Dominique Borrione, IMAG, France (Room: OAXACA) |
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17:00 – 19:00 |
VLSI-SoC 2014 TPC Meeting |
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Organizer: Luc Claesen, Hasselt University Belgium and Maria Teresa Sanz, INAOE, Mexico (Room: OAXACA) |
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Monday, 6 October 2014 |
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8:30 – 9:00 |
Registration |
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9:00 – 9:30 |
Welcome and Opening |
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General Chairs, Program Chairs, Local Officials |
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9:30 – 10:30 |
Keynote: “Design Automation Beyond High-Level Synthesis” |
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Jason Cong, UCLA, USA |
High-level synthesis (HLS) is gaining wide acceptance in recent years. One example is the success of wide adoption of the Xilinx Vivado HLS tool (originated from the UCLA xPilot project and its spin-off AutoESL), which now has thousands of users worldwide. Modern HLS tools can generate efficient RTL code from behavior level C/C++ specifications with the quality that is comparable to manual RTL designs. But the quality of result may be highly dependent on how the input C/C++ is written. Our recent research focuses on source-code level transformation and optimization to generate HLS-friend behavior specifications. In this talk, I shall present our work in this direction, including polyhedral-based data reuse optimization and code generation, uniform and non-uniform memory partitioning, and simultaneous computation and communication optimization. Experimental results show that these transformations and optimization techniques lead to much better HLS results.
About the Speaker:
Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor’s Professor at the Computer Science Department of University of California, Los Angeles, the director of Center for Domain-Specific Computing (CDSC), and co-director of UCLA/Peking University Joint Research Institute in Science and Engineering. He served as the chair of the UCLA Computer Science Department from 2005 to 2008.
Dr. Cong’s research interests include synthesis of VLSI circuits and systems, programmable systems, novel computer architectures, nano-systems, and highly scalable algorithms. He has over 390 publications in these areas, including 10 best paper awards and the 2011 ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. He is the recipient of the 2010 IEEE Circuits and System (CAS) Society Technical Achievement Award "For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation."
Dr. Cong has graduated 31 PhD students. Many of them are now faculty members in major research universities, including Cornell, Georgia Tech., Peking University, Purdue, SUNY Binghamton, UCLA, UIUC, and UT Austin. Four of them were co-founders, together with Dr. Cong, of two startups originated from UCLA – Aplus Design Technologies, which developed the first FPGA physical synthesis tool (acquired by Magma in 2003, now part of Synopsys) and AutoESL Design Technologies, which led to the most widely used high-level synthesis tool Vivado HLS (acquired by Xilinx in 2011). Others are in key R&D or management positions in various companies related to the information technologies, such as Amazon, Bloomberg, Broadcom, Cadence, Facebook, Google, IBM, Intel, Mentor Graphics, Micron, Synopsys, and Xilinx.
10:30 – 11:00 |
Coffee Break |
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11:00 – 12:30 |
Room: Oaxaca |
Room: Yucatán |
M1A (Regular Session): DSP & Image Processing SoC |
M1B (Regular Session): Design for Variability & Reliability |
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1. Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras Kerem Seyid, Omer Cogal, Vladan Popovic, Hossein Afshari, Alexandre Schmid and Yusuf Leblebici. EPFL, Lausane, Switzerland. |
1. Evaluation of Digital Ternary Stimuli for Dynamic Test of Sigma-Delta ADCs Matthieu Dubois, Haralampos-G. Stratigopoulos, Salvador Mir and Manuel J. Barragan. TIMA Laboratory, (CNRS – Universite Grenoble Alpes), France. |
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2. VLSI Design of a Parallel MCMC-based MIMO Detector with Multiplier-Free Gibbs Samplers Dominik Auras, Uwe Deidersen, Rainer Leupers and Gerd Ascheid. RWTH Aachen University, Germany. |
2. Dynamic Programming-Based Lifetime Aware Adaptive Routing Algorithm for Network-on-Chip Liang Wang1, Xiaohang Wang2 and Terrence Mak1. 1The Chinese University of Hong Kong, 2Guangzhou Institute of Advanced Technology, China. |
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3. Reconfigurable Forward Homography Estimation System for Real-Time Applications Vladan Popovic and Yusuf Leblebici. |
3. Reducing Test Time for 3D-ICs by Improved Utilization of Test Elevators Sreenivaas Muthyala and Nur Touba. University of Texas at Austin, USA. |
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12:30 – 15:30 |
Lunch |
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15:30 – 17:30 |
Room: Oaxaca |
Room: Yucatán |
M2A (Regular Session): Multicore Processors & NoC |
M2B (Regular Session): SoC Design & Verification Strategies |
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1. Energy-Efficient Partitioning of Hybrid Caches in Multi-Core Architecture |
1. A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Verification Flow |
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2. Crossbar Replication vs. Sharing for Virtual Channel Flow Control in Asynchronous NoCs: a Comparative Study |
2. A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms |
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3. A Quantum Algorithm Processor Architecture based on Register Reordering |
3. Framework for Simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability |
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4. Through Silicon Via Placement and Mapping Strategy for 3D Mesh Based Network-on-Chip |
4. Towards Energy Effective LDPC Decoding by Exploiting Channel Noise Variability |
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17:30 – 19:00 |
Room:Chiapas and Yucatán |
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M3AB Poster Session and Ph.D. Forum |
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Detailed placement accounting for technology constraints |
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Power dissipation effects on 28nm FPGA-Based SoC neutron sensitivity |
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Deconvolution Algorithm Dependencies of Estimation Errors of RTN Effects on Subnano-Scaled SRAM Margin Variation |
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Inference of packet types in channels of micro-architectual communication networks |
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Implementation of Power Efficient Multicore FFT Datapaths by Reordering the Twiddle Factors |
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Decimal Engine for Energy-Efficient Multicore Processors |
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Complementary logic interface for high performance optical computing with OLUT |
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AES Design Space Exploration New Line for Scan Attack Resiliency |
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Soft Error Effects Analysis and Mitigation in VLIW Safety-Critical Applications |
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Circuit to reduce Gate Induced Drain Leakage in CMOS output buffers |
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Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs |
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Reconfigurable SOC for Ultra Low Power Passive Sensor System Applications |
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A Novel Non-minimal/Minimal Turn Model for Highly Adaptive Routing in 2D NoCs |
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Automated Functional Coverage Directed for Complex Digital Systems |
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Study of On-Chip Vias of Resonant Rotary Traveling Wave Oscillators |
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Enhancing Hardware Trojan Detection through Security Aware Design |
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Configuration and programming of ASICs for embedded control using model-based design |
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Modeling, Analysis and Exploration of LAYERS: A 3D Computing Architecture |
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Sigma-Delta ADCs for Software-Defined-Radio Applications |
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Advances on the State of the Art in QDI Design |
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19:30 – 21:30 |
Social Event 1 |
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Welcome Cocktail |
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Tuesday, 7 October 2014 |
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9:00 – 10:00 |
Keynote: “Heterogeneous Self-Powered 3D ICs - key concepts and developments” |
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Maciej Ogorzalek, Jagiellonian University Krakow, Poland |
Since the launch of the Smart-dust project aimed at development of millimeter-scale devices which contain sensors, processors, communication and power supply parts considerable advance has been made in technologies which might be useful in construction of self-contained and self-powered devices. The advent of 3D chip technology and possibility of inclusion of heterogenous technologies allows for audacious trials possibly outperforming any solutions proposed so far.
Here new technologies for production of ultra-capacitors (of capacitances in the range of 1000 Farads per cubic centimeter) based on new nano materials can play a major role. As possible energy sources the revolutionary nano-batteries based on nano-wires and nano-tubes attract a lot of attention along with a wide range of energy scavenging devices that could be used.
Unfortunately such components can not be fabricated in silicon and possible integration into one chip brings many new problems and challenges.
In particular we describe the idea of a system composed of a functional part (processing layer) + energy storage device (ultra cap)+ energy source (fractal battery) all integrated into one 3D chip.
About the speaker:
Maciej Ogorzalek (IEEE Fellow -1997) is Professor of Electrical Engineering and Computer Science and Head of the Department of Information Technologies, Jagiellonian University Krakow, Poland. He held several visiting positions in Denmark, Switzerland, Germany, Spain, Japan, Hong Kong. 2006-2009 he held the Chair of Biosignals and Systems, Hong Kong Polytechnic University under the Distinguished Scholars Scheme. Author or co-author of over 250 technical papers published in journals and conference proceedings, author of the book Chaos and Complexity in Nonlinear Electronic Circuits (World Scientific, 1997). He served as Editor-in-Chief of the Circuits and Systems Magazine 2004-2007, Associate Editor for the IEEE Transactions on Circuits and Systems Part I, 1993-1995 and 1999-2001, he was elected Member of the Editorial Board Proceedings of the IEEE 2004-2009. He serves also as an Associate Editor International Journal of Bifurcation and Chaos (since 2004), Journal of the Franklin Institute (1997), and Member of the Editorial board ofthe International Journal of Circuit Theory and Applications (2000-). He served the IEEE Circuits and Systems Society in various capacities including 2008 Society President. He was CAS Society Distinguished Lecturer (2004-2005) and received the 2002 Guillemin-Cauer Award and IEEE-CAS Golden Jubilee Award. In 2012 he has been elected member of the European Academy of Sciences. He was co-organizer of the CAS-FEST event devoted to Heterogeneous nano-circuits and systems at ISCAS 2012 and guest editor of a special issue of IEEE Journal of Emerging and Selected Topics in Circuits and Systems (with Giovanni DeMicheli and Subasish Mitra) devoted to this subject.
10:00 – 10:30 |
Coffee Break |
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10:30 – 12:30 |
Room: Oaxaca |
Room: Yucatán |
T1A (Regular Session): SoC Optimization & Synthesis |
T1B (Special Session): Advances in integrated systems security: from attack models to system architecture and countermeasures |
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Organizer: Régis Leveugle, TIMA Laboratory, Grenoble, France |
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1. Logic synthesis and verification on fixed topology |
1. Electromagnetic analysis, deciphering and reverse engineering of integrated circuits |
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2. Design and Optimization of Multiple-Mesh Clock Network |
2. ElectroMagnetic Analysis and Fault Injection onto Secure Circuits |
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3. Self Similarity and Interval Arithmetic Based Leakage Optimization in RTL Datapaths |
3. Laser-induced fault effects in security-dedicated circuits |
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4. Backplane/FDA Correlation –FDA replacing Commercial Backplanes for SoC Ethernet Electrical Validation |
4. Trusted computing using enhanced manycore architectures with cryptoprocessors |
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12:30 – 16:00 |
Lunch |
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16:00-20:00 |
Social Event 2 |
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Please be at the Quetzal lobby five minutes before 4:00 pm, with your tickets in hand. |
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Wednesday, 8 October 2014 |
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9:00 – 10:00 |
Keynote: “SoC's paving the way of Software Defined Radio for the Masses.” |
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Frederick Harris, San Diego State University, USA |
About the Speaker:
Fredric J Harris holds the Signal Processing Chair of the Communication Systems and Signal Processing Institute at San Diego State University where since 1967 He has taught courses in Digital Signal Processing and Communication Systems. He holds 20 patents on digital receiver and DSP technology and lecture throughout the world on DSP applications. He consults for organizations requiring high performance, cost effective DSP solutions. He is an adjunct member of the IDA-Princeton Center for Communications Research.
He has written over 200 journal and conference papers, the most well known being his 1978 paper “On the use of Windows for Harmonic Analysis with the Discrete Fourier Transform”. He is the author of the book Multirate Signal Processing for Communication Systems and he has contributed to a number of other books on DSP applications including the “Source Coding” chapter in Bernard Sklar’s 1988 book, Digital Communications and the “Multirate FIR Filters for Interpolation and Resampling” and the “Time Domain Signal Processing with the DFT” chapters in Doug Elliot’s 1987 book Handbook of Digital Signal Processing, and “A most Efficient Digital Filter: The Two-Path Recursive All-Pass Filter” and the “Ultra Low Phase Noise DSP Oscillator” Chapters in Rick Lyons 2012 second edition book Streamlining Digital Signal Processing.
In 1990 and 1991 he was the Technical and then the General Chair of the Asilomar Conference on Signals, Systems, and Computers and was Technical Chair of the 2003 Software Defined Radio Conference and of the 2006 Wireless Personal Multimedia Conference. He then, became a Fellow of the IEEE in 2003, cited for contributions of DSP to communications systems. In 2006 He received the Software Defined Radio Forum’s “Industry Achievement Award”. His 2006 paper and again his 2011 paper at the SDR conference were selected for the best paper award as were his paper at the Autotestcon-2011 conference and his paper at WPMC-2022. He served as the Editor-in-Chief of the Elsevier DSP Journal.
He is a traditional absent-minded professor who drives secretaries and editors to distraction by requesting strictly lower case letters to spell his name. For amusement, he roams the world collecting old toys and slide-rules and riding old railways.
10:00 – 10:30 |
Coffee Break |
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10:30-12:30 |
Room: Oaxaca |
Room: Yucatán |
W1A (Regular Session): Novel Devices & MEMS |
W1B (Regular Session): Memory Architectures & NoC |
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1. Simulated Annealing-based Placement for Microfluidic Large Scale Integration (mLSI) Chips |
1. A Low Power 720p Motion Estimation Processor with 3D Stacked Memory |
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2. Multi-terminal PCB Escape Routing for Digital Microfluidic Biochips using Negotiated Congestion |
2. Improved Read and Write Margins Using a Novel 8T-SRAM Cell |
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3. Silicon Photonics Design Rule Checking: Application of a Programmable Modeling Engine for Non-Manhattan Geometry Verification |
3. A Novel Non-minimal Turn Model for Highly Adaptive Routing in 2D NoCs |
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4. Low-power High-Speed Current Mode Logic using Tunnel-FET |
4. Scalable and Energy-Efficient Reconfigurable Accelerator for Column-wise Givens Rotation |
12:30 – 15:30 |
Lunch |
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15:30-17:00 |
Room: Oaxaca |
Room: Yucatán |
W2A (Regular Session): Fault Tolerance |
W2B (Special Session): Spin-electronics: from digital to analogue functions towards tomorrow's Systems on Chip |
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Organizers: Guillaume Prenat, Spintec, CEA-INAC/CNRS/University of Grenoble-Alpes, France |
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1. Fast Accurate Evaluation of Register Lifetime and Criticality in a Pipelined Microprocessor |
1. Advances and Challenges in STT-MRAM technology |
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2. Realizing a Security Aware Selective Triple Modular Redundancy Scheme for Robust Integrated Circuits |
2. MRAM the future of System on Chip? |
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3. A Novel Metric for Evaluating Combinational Circuit Vulnerability to Soft Errors |
3. Nano-scale microwave devices based on magnetic tunnel junctions |
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4. MLU based Magnetic sensors |
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17:00-17:30 |
Coffee Break |
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17:30-18:00 |
Plenary Closing Remarks |
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Chair: General Chairs, Program Chairs |
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Fringe meetings (by invitation only) |
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18:00-19:00 |
Concluding TPC meeting |
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Room: Oaxaca Maria Teresa Sanz, INAOE, Mexico. |
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19:00-20:00 |
VLSI-SoC 2016 Planning meeting |
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Room: Oaxaca |